1. Field of the Invention
The present invention relates to flash EPROM's and a method for preventing sub-threshold leakage in flash EPROM cells, and more particularly, a method for preventing sub-threshold leakage in flash memory cells during overerase Vt repair operations, read operations and verify operations.
2. Description of the Related Art
Programming operations in an EPROM-type flash memory require injecting electrons into a floating gate to increase the cell's threshold voltage Vt through a channel-hot-electron (CHE) process, while erase operations involve removing electrons from the floating gate of the EPROM to lower the cell's threshold voltage Vt through Fowler-Nordheim tunneling.
During the erase operation, however, overerasing can occur if too many electrons are removed, lowering the cell's Vt below ground to a negative value and causing the cell to be in a permanently "on" condition. When conventional erase techniques are used, such a cell cannot be shut off, causing undesired current leakage in the bitline, which can result, thereafter, in false memory readings due to cells existing that have been improperly erased.
A commonly used operating voltage Vdd in flash memories is 5V, and for this Vdd, a Vt between 0.5V and 3V is often considered a data "1" and a Vt greater than 6V is often considered a data "0." FIG. 1 illustrates a typical distribution of cells after an erase operation of certain cells in a bitline in a left column, with the change in the distribution of the cells' Vt versus time in a given bitline during a conventional Vt repair operation in the right column.
After an erase operation, to correct an overerased cell, the cell's negative Vt must be programmed back to the positive level, usually to around 1V, in a negative Vt correction process, also known as Vt repair. FIG. 1 is provided to assist in understanding the Vt voltages of the cells through the Vt repair process. Regions A, B, C and D have been identified for purposes of defining different Vt characteristics. Thus, Region B corresponds to a region in which cells having a Vt within this region may experience undesired hot-hole injection. Region C corresponds to a region in which cells having a Vt within this region may experience channel-hot-electron injection and represent the Vt range of over-erased cells needing Vt repair; that is, cells having a negative Vt. The Vt for region C cells can fall as low as -3V. Cells within Regions A and D will experience no such injection, but differ in that Region D corresponds to a data "0" program state, whereas region A primarily corresponds to an uncertain state between a data "1" and a data "0", although as illustrated in FIG. 1, a lower portion of the band within Region A may correspond to a data "1." The uncertain state of Region A can also be viewed as a region corresponding to cells with a Vt that was improperly erased and verified. The voltage gap, uncertain region within Region A is purposefully included to separate the data "1" and data "0" states so cells having different data can easily be differentiated. It should also be noted that the particular voltage separating regions A and B corresponds to the UV erase voltage Vt*, which, for the FIG. 1 known embodiment, corresponds to 2V.
One proposed method for avoiding over-erased cells is to pre-program selected cells at a higher Vt before the erasing operation is carried out, erase the cells, and then perform the Vt repair operation on any cells that have been overerased. Preprogramming the cell's Vt to a higher positive level, such as greater than 6V for the embodiment of FIG. 1 referenced above, before carrying out the erase operation reduces the chances (and usually the number) of overerased cells, but because the pre-programmed Vt and other cell characteristics can vary between cells, there is still an unpredictable number of overerased cells (that is, cells having a negative Vt) after the erase operation despite the cautionary pre-programming step. Thus, the negative Vt of these over-erased cells still have to be programmed back to a positive Vt, such as about 1V for the FIG. 1 embodiment being described, in a Vt repair operation, notwithstanding the additional pre-programming step before erasure. Further, in the case of block erasure, many cells in different wordlines are erased together as an entire block without differentiating between cells requiring erasing and those that do not in a particular group. As a result, cells not requiring any erasing or repair may suffer Vt repair disturbance, causing unnecessary Vt voltage drops in cells that were originally acceptable before the Vt repair operation. If the initial Vt of a particular cell was positive, but still lower than the UV erase voltage Vt*, the Vt repair disturbance may cause the Vt of that cell to become negative and consequently require later Vt repair even though the cell was acceptable before the Vt repair operation began. Clearly, these extra Vt repair operations increase processing time.
Another proposed method for remedying the over-erasure problem is described in U.S. Pat. No. 5,521,867 to Chen et al. Chen describes a circuit that attempts to converge the erase threshold voltage distribution in the memory cells to a selected steady-state threshold voltage that is higher than the self-convergence steady state threshold voltage, which is the Vt. The '867 reference teaches coupling a first voltage source to the bitlines in the memory and coupling a second voltage source to the wordlines to converge the threshold voltages of erased memory cells to the same steady-state threshold voltage. The steady-state threshold voltage Vth* is selected to minimize the number of cells receiving hot hole injection; in FIG. 8 of the Chen patent, 1V is selected. This method, however, still does not address the problem of protecting cells from Vt repair disturbance or degradation; in fact, it appears that the '867 patent accepts some oxide and Vt degradation through hole injection as a necessary part of the convergence process, as shown in FIG. 8 (col. 10, lines 40-57 in Chen).
Referring now to FIGS. 1 and 2, the prior art method applies 0V to all wordlines and +5V to the selected bitline, regardless of whether the cells in the bitline need Vt repairing or not. As a result, cells 100 and 108, which have Vt's in regions A and D respectively, are shut off. Cell 102, in region B, experiences oxide and Vt degradation as hot hole injection lowers the cell's 102 Vt toward 0V. For overerased cells 104 in region C, which have negative Vt's, avalanche hot electron injection is used to repair the cells' Vt, but the Vt repair process tends to be very slow. Although this prior art method attempts to converge the Vt's of all the cells to a fixed, final voltage of 0V, FIG. 1 shows that after the Vt repair operation, the Vt's of the cells can still range from -1V to +1V, depending on each cell's characteristics. These variations can cause undesirable false readings in the flash memory. Further, cells may even have a Vt between 3V and 6V, thus falling into region A due to an improper erase operation. As noted above, these region A cells are unacceptable because they are neither data "1" nor data "0" cells. In short, prior art erase and Vt repair operations cannot accurately place each individual cell's Vt into an acceptable condition because all operations are done collectively on multiple cells. Further, fluctuations in the cells' Vt due to hot-hole injection and subthreshold current leakage make it difficult to evaluate and correct the Vt of each individual cell.
Prior art methods for Vt repair present numerous other problems as well. At most, only two wordline voltages are applied simultaneously during Vt repair, one to non-selected wordlines and one to selected wordlines and, as noted above, a single wordline voltage is applied to all selected erased wordlines during Vt repair. No attempt is made to generate a wordline voltage for shutting off sub-threshold leakage in non-selected wordlines cells with large negative Vt's. In addition, the Vt repair operation in many prior art methods is collectively performed on all cells in a selected bitline, regardless of whether the cells actually need Vt repair. Known methods also fail to address how the resultant Vt drop caused by subthreshold current leakage and Vt repair process disturbance in other cells can be prevented. Further, in prior art methods, the wordline voltage for the cells selected for Vt repairing usually ranges between -1V and +1V, which is not low enough to shut off the over-erased cells with Vts less than -1V and yet not high enough to return them quickly to a controllable, precise, positive Vt required for normal read operations. Convergence processes pose additional problems because the erase speed can be extremely slow, even slower than 100 ms, and the correlation between the measurement and real bitline convergence is un-matched. Also, the wordline voltage needed to increase the convergence of Vt*, in practice, tends to vary as the cell characteristics vary, making it difficult to converge Vt* as a practical matter.
There is a need for an EPROM-type flash memory that not only Vt repairs overerased cells, but also protects other cells from Vt disturbance or degradation caused by the Vt repair process. There is also a need for an erasing and Vt repair process for low Vdd operations that has high speed, low current consumption, and achieves longer endurance cycles than conventional Vt repair processes for EPROM-type flash memories.
Subthreshold leakage can also occur during a read or verify operation, particularly when the selected bitline voltage is high and the number of non-selected but low Vt cells are too great. The higher bitline voltage and greater number of non-selected by low Vt cells in the bitline will increase the sub-threshold leakage and result in false readings.